The present invention relates to a semiconductor nonvolatile read only memory device and, more particularly, to a semiconductor nonvolatile read only memory device with a high-speed access time.
At present, semiconductor nonvolatile read only memory devices (to be referred to as ROMs hereinafter) have frequently been used for storing computer programs and fixed data. The ROM is usually comprised of memory cell transistors, X and Y addresses, decoders, an output buffer, and the like. Referring to FIG. 1, the construction and operation of a conventional ROM of the direct decoding system constituted of four X address buffers, will now be described. Assume that the transistors shown in FIG. 1 are all n-channel MOS transistors.
An address buffer 10 is controlled by chip enable signals CE* and CE* (the inverted signal of signal CE*). Address buffer 10, in a stand-by mode, produces address signals A1* and A1* of low level and, in an active mode, wave-shapes an address signal A1 to produce address signal A1* and A1* of low or high level. Three other address buffers (not shown) have each substantially the same construction. A row decoder 12 is comprised of enhancement type (to be referred to as E-type hereinafter) MOSFETs 14, 16, 18 and 20, and depletion-type (to be referred to as D-type hereinafter) MOSFETs 22, 24 and 26. D-type MOSFET 22 which is supplied at the drain node 28 with a power source voltage Vcc has its gate and source connected to a decode node 30, to which power source voltage Vcc is applied when row decoder 12 is selected. In a writing operation, D-type MOSFET 24 is applied at a gate node 32 with a low level signal to disconnect node 30 from a word line node 34, while in a reading operation, is applied at gate node 32 with a high level signal to connect nodes 30 and 34. D-type MOSFET 26 has the drain connected to a write terminal 36 to charge, in a writing operation, word line node 34 up to a write potential Vpp when node 34 is selected. Address signals from the address buffers are inputted to the gates of MOSFETs 14, 16, 18 and 20 as follows: an address signal A1* is applied to the gate of MOSFET 14; an address signal A2* to the gate of MOSFET 16; an address signal A3* to the gate of MOSFET 18; and address signal A4* to the gate of MOSFET 20. Since, in a stand-by mode, low-level address signals are applied to the gates of MOSFETs 14 to 20, these FETs are turned OFF, allowing node 30 to become at high level. In an active mode, decode node 30 becomes at high level when the row decoder is selected, and becomes at low level when the decoder is not selected. The sources of MOSFETs 14 to 20 are grounded. Word line node 34 is connected to the gate of memory cell transistor 38, which, in a writing operation, is applied with a high voltage to perform data write. Memory cell transistor 38 has the source connected to ground and the drain to a read common node 40. Read common node 40 is connected to a sense amplifier (not shown) and, in a stand-by mode, is disconnected from the amplifier, thereby causing the potential at node 40 to become in a floating state.
Referring to FIGS. 2(A) to 2(D), the operation of the ROM thus constructed will now be described. Assume that data has already been written into memory cell transistor 38. Since read common node 40 is so provided to be in a floating state in a stand-by mode, the leak of charge from memory cell transistor 38 causes the potential at read common node 40 to drop to the ground potential. Under the condition that read common node 40 is at zero level, the mode of the chip enable signal CE applied to a chip enable buffer (not shown) is changed from a stand-by state to an active state, as shown in FIG. 2(A). A word line node other than word line node 34 is then selected. As a result, the potential at word line node 34 changes from a high level to a low level, as shown in FIG. 2(B). This potential change causes a potential at common node 40 to decrease from zero to minus value as indicated by RA in FIG. 2(C), because of the coupling by the capacitance present between nodes 34 and 40 (more specifically, the capacitance between all the other word lines than the selected word line and the read common node). For this reason, when a data of "0" is written into the memory cell transistor selected, the potential at common node 40 rises as indicated by RB in FIG. 2(C). When a data of "1" is written into the memory cell transistor, the potential at common node 40 rises as indicated by RC in FIG. 2(C). Since the potential at common node 40 has fallen to the minus region, a potential rising rate of "0" data is different from that of "1" data. Consequently, a data output signal from a data output buffer (not shown) connected to the sense amplifier amplifying a sensed signal from the common node changes along a curve DB in reading "0" as shown in FIG. 2(D), and changes along a curve DC in reading "1". As described above, the ROM shown in FIG. 1 has a drawback that the access time depends on data stored in the memory cell transistor, more particularly, the access time for " 0" data is rather long.
To solve this problem, the ROM arranged as shown in FIG. 3 has been proposed. FIG. 3 shows an arrangement of a major portion of the ROM.
Referring to FIGS. 4(A) to 4(E), the operation of the ROM thus constructed will now be described. In a stand-by mode, low level signals, for example, A1*, A2*, A1* and A2*, are applied from address buffers to the gates of E-type MOSFETs 42 to 48, which are turned OFF, causing a node 50 to become at high level. As a result, a D-type MOSFET 52, having the gate and source connected to node 50, is turned ON, and drain node 54 to which voltage Vcc is applied supplies voltage Vcc to node 50. The high level signal at node 50 is delayed by a delay circuit 60 constituted of a resistor 56 and a capacitor 58 and is applied to the gate of an E-type MOSFET 62, which is then turned ON. The drain of E-type MOSFET 62 is connected to a read common node 64. Read common node 64 is connected to a sense amplifier (not shown) which amplifies the sensed signal produced from node 64.
A chip enable signal CE of low level is inputted to a chip enable buffer (not shown) (FIG. 4(A)) and the ROM is brought to an active mode. In an active mode, any one of E-type MOSFETs 42 to 48 is turned ON, causing node 50 to drop to a low level potential (FIG. 4(B)). This potential change is delayed for a period of time D by delay circuit 60 as shown in FIG. 4(C) and then is applied to the gate of E-type MOSFET 62. Although the potential at a selected read common node once falls to a minus value as shown in FIG. 4(D), it is restored to the zero potential, as represented by RE in FIG. 4(D), by supplying charge from the ground because E-type MOSFET 62 remains ON for the delay time D of delay circuit 60. This potential restoration makes it possible to compensate the difference between the access time when the memory cell transistors store "0" data and that when they store "1" data. As a result, the signal produced from a data output buffer (not shown) connected to the sense amplifier has similar access times for "0" read (curve DB) and "1" read (curve DC) as shown in FIG. 4(E). Although, having the advantage mentioned above, the ROM shown in FIG. 3 has a drawback that the delay time D of delay circuit 60, during which data access is impossible, elongates access time.